Product Perfect

**The Make utility**, also known as **Makefile**, is a simple build automation tool that automates the creation of executables from source code. Introduced in 1977 by Stuart Feldman at Bell Labs, it was originally written in Fortran. Make is used to maintain complex software builds by automating the process of determining which files need to be recompiled and linking them together. **Make works by reading a file called the** **makefile**, which contains a list of targets and dependencies. Targets are the files that you want to create, and dependencies are the files that need to be created before the target can be built. When Make is run, it will first check to see if the target is up-to-date with the dependencies. If the target is not up-to-date, Make will execute the commands listed in the makefile to create the target. **Make is a powerful tool that can save you a lot of time when building software.** It is especially useful for projects with a lot of dependencies, as it can help y

Ask the right questions secure the right Makefile talent among an increasingly shrinking pool of talent.

First 20 minutes

General Makefile app knowledge and experience

The first 20 minutes of the interview should seek to understand the candidate's general background in Makefile application development, including their experience with various programming languages, databases, and their approach to designing scalable and maintainable systems.

How would you define a Makefile?

A Makefile is a file containing a set of directives used by a make build automation tool to generate a target/goal.

What are the basic components of a Makefile?

The basic components of a Makefile are targets, prerequisites, and recipes.

How would you specify a target in a Makefile?

A target is specified in a Makefile by writing the target name followed by a colon and then the prerequisites for that target.

What are prerequisites in a Makefile?

Prerequisites in a Makefile are files that must exist before a target can be executed.

How would you define a recipe in a Makefile?

A recipe in a Makefile is a series of commands that are executed when a target is built.

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What you’re looking for early on

Has the candidate demonstrated a deep understanding of Makefile syntax and rules?

Does the candidate seem familiar with different operating systems?

Can they articulate the role of a Makefile in software development?

Has the candidate shown the ability to debug Makefiles?

Next 20 minutes

Specific Makefile development questions

The next 20 minutes of the interview should focus on the candidate's expertise with specific backend frameworks, their understanding of RESTful APIs, and their experience in handling data storage and retrieval efficiently.

Describe the difference between explicit and implicit rules in a Makefile.

Explicit rules in a Makefile define commands for a specific target, while implicit rules define commands for a class of targets.

How would you use variables in a Makefile?

Variables in a Makefile can be used to simplify and make the Makefile more readable. They are defined using the equals sign and can be referenced using the $(VAR_NAME) syntax.

What are pattern rules in a Makefile?

Pattern rules in a Makefile are a type of implicit rule that can be applied based on the matching of the target and prerequisites.

How would you use functions in a Makefile?

Functions in a Makefile can be used to manipulate variables and can be called using the $(function arguments) syntax.

Describe the difference between automatic and user-defined variables in a Makefile.

Automatic variables in a Makefile are set by make and contain useful information, while user-defined variables are set by the user.

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At this point, a skilled Makefile engineer should demonstrate strong problem-solving abilities, proficiency in Makefile programming language, and knowledge of software development methodologies. Red flags include lack of hands-on experience, inability to articulate complex concepts, or unfamiliarity with standard coding practices.

Digging deeper

Code questions

These will help you see the candidate's real-world development capabilities with Makefile.

What does this simple Makefile do?
all:
	gcc main.c -o main
This Makefile compiles the 'main.c' file using the gcc compiler and outputs an executable named 'main' when the 'make all' command is executed.
What does the wildcard function do in the following Makefile?
SRCS := $(wildcard *.c)
OBJS := $(SRCS:.c=.o)
all: $(OBJS)
The wildcard function in this Makefile is used to collect all the '.c' files in the current directory. The '.c' files are then converted to '.o' (object) files. The 'all' target depends on these '.o' files.
What does the foreach function do in the following Makefile?
SRCS := file1.c file2.c file3.c
OBJS := $(foreach src,$(SRCS),$(src:.c=.o))
all: $(OBJS)
The foreach function in this Makefile is used to iterate over the list of source files ('SRCS'). For each source file, it replaces the '.c' extension with '.o' to generate the list of object files ('OBJS'). The 'all' target depends on these '.o' files.
What does the .PHONY rule do in the following Makefile?
.PHONY: clean
all:
	gcc main.c -o main
clean:
	rm -f main
The .PHONY rule in this Makefile is used to specify that 'clean' is not associated with a file. This way, 'make clean' will always execute the associated commands (in this case, removing the 'main' executable), even if there is a file named 'clean' in the directory.

Wrap-up questions

Final candidate for Makefile Developer role questions

The final few questions should evaluate the candidate's teamwork, communication, and problem-solving skills. Additionally, assess their knowledge of microservices architecture, serverless computing, and how they handle Makefile application deployments. Inquire about their experience in handling system failures and their approach to debugging and troubleshooting.

How would you handle errors in a Makefile?

Errors in a Makefile can be handled using the -k or --keep-going option, which tells make to continue as much as possible after an error.

What are the special built-in target names in a Makefile?

Special built-in target names in a Makefile include .PHONY, .SUFFIXES, .DEFAULT, .PRECIOUS, .INTERMEDIATE, .SECONDARY, .SECONDEXPANSION, .DELETE_ON_ERROR, .IGNORE, .LOW_RESOLUTION_TIME, .SILENT, and .EXPORT_ALL_VARIABLES.

How would you use conditional directives in a Makefile?

Conditional directives in a Makefile can be used to conditionally include or exclude parts of the Makefile based on the values of variables.

Makefile application related

Product Perfect's Makefile development capabilities

Beyond hiring for your Makefile engineering team, you may be in the market for additional help. Product Perfect provides seasoned expertise in Makefile projects, and can engage in multiple capacities.

Makefile Consultive assessments

Makefile Application Conversion Assessment Makefile Application Integration Assessment Makefile Data & Database Integration Assessment

Custom Makefile development projects

Custom Makefile App Conversion Makefile Custom App Development Process App UI Design for Makefile Facelifts

Hiring guide for Makefile Engineers

Makefile Developer Hiring Guide

What you’re looking for early on

The ideal back-end app developer

What you’re looking to see on the Makefile engineer at this point.

Makefile Consultive assessments

Custom Makefile development projects